Semiconductor circuits are required to withstand a relatively high voltage in many different kinds of applications. An example of one such application is found in the subscriber line circuits of telephone exchanges. In older Swedish telephone exchanges, the line to a subscriber was required to have an applied voltage of 48 volts, and modern subscriber line circuits in semiconductor techniques are adapted to these voltages. Higher voltages are required in other countries, for instance 68 volts in Germany, while other applications of semiconductor circuits may use still higher voltages, for instance voltages of 400 volts or more.
One problem with these relatively high voltages is that the electrical field strength may exceed the critical field strength of the semiconductor material in certain regions of a component. This can result in a current breakthrough which destroys the semiconductor material if the current is not limited. The same problem of high field strength also occurs in very small and fast semiconductor components intended for calculating or computing circuits. Although these components are connected to low voltages, on the order of 3 to 5 volts, the small extensions of the components enable the electrical field strength to reach high values.
In certain applications, the problem of high electric field strength is pronounced at the surface of a semiconductor component, as described in an article in IEEE, Proceedings from IEDN, 1979, pages 238-241, by J. A. Appels and H. M. J. Vaes: "High Voltage Thin Layer Devices (Resurf Devices)", this article being hereby incorporated by reference in the present description. The semiconductor component has a surface layer in which there is included a PN-junction in which the critical field strength of the material is reached at a given applied voltage. The surface layer is weakly doped on one side of the PN-junction and this weakly doped part can be depleted of charge carriers by making the surface layer relatively thin. The applied voltage is distributed over a long distance along the component surface, so that the maximum field strength will adopt a value beneath the breakdown field strength. The phenomenon is well known within semiconductor technology and has been given the personal acronym RESURF (REduced SURface Field). The resurf technique is described in more detail in an article in Philips J. Res. 35, 1-13, 1980, J. A. Appels, et al: "Thin Layer High-Voltage Devices". This article is also hereby incorporated by reference in the present description.
U.S. Pat. No. 4,409,606 describes the resurf technique applied to a transistor. A relatively thin semiconductor layer in which the transistor is formed is mounted on a semiconductor substrate. The substrate and the layer form a PN-junction and a heavily doped region in the PN-junction is arranged beneath one transistor connection. This junction is reverse biased and the thin semiconductor layer is depleted of charge carriers up to the layer surface, along a path which extends between the heavily doped region and the second transistor connection. A good degree of safety against current breakthrough is obtained when this path is made sufficiently long. Such application of the resurf technology deals with those problems that occur with breakdown voltage at the base of a bipolar transistor due to current amplification, often referred to as common base amplification and designated .alpha..sub.o in the literature. A similar arrangement is also described in U.S. Pat. No. 4,639,761.
European Patent Application No. A1-0,086,010 describes a transistor which is similar to the transistor described in the two aforesaid U.S. patents. This latter transistor, however, lacks the heavily doped region in the PN-junction, and the layer in which the transistor is formed has an elevated doping concentration. It is therefore difficult to fully deplete this layer of charge carriers and an isolated electrode is placed over those regions to be depleted of charge carriers in order to achieve total depletion.
In the case of the two aforesaid U.S. patents and the European patent application, the transistor is connected to the semiconductor substrate of the device through the aforesaid PN-junction. The transistor is delimited laterally by deep, heavily doped regions which have reverse biased PN-junctions. one drawback with the thus delimited transistors is that they take up a large amount of space in the substrate. This drawback is avoided with an arrangement according to European Patent Application No. A1-0,418,737, which describes transistors on a common substrate that are dielectrically isolated from one another. A surface of a semiconductor substrate is oxidized to form an isolating layer on which a relatively thin wafer of epitaxial semiconductor material is mounted. This epitaxial wafer has etched therein grooves which extend down to the isolating layer. The side surfaces of the grooves are oxidized and the grooves filled with polycrystalline semiconductive material. Components are formed in the dielectrically isolated, box-like regions thus formed. These components have an external connection which is connected to a heavily doped connecting layer beneath respective components on the box bottom, in direct abutment with the isolating oxide layer.
European Patent Application No. A2-0,391,056 describes an alternative method of forming a semiconductor substrate with dielectrically isolated regions. The isolated regions are produced by repeatedly etching the substrate and coating with semiconductor material. The dielectric isolation is comprised of oxidized semiconductor material. The regions have a weakly doped area in which the actual component is formed and a heavily doped connection layer which is located beneath said component and lies against the dielectrically isolating layer.
U.S. Pat. No. 4,868,624 discloses a monolithic semiconductor transistor structure wherein the active collector region of a bipolar-junction transistor is physically and operatively merged with the channel region of a junction field-effect transistor, providing a composite circuit which approximates a cascode configuration. By controlling the integral of the net impurity doping concentration to various active regions of the device, the active collector region of a bipolar-junction transistor configuration is made sufficiently thin so as to simultaneously function as an active collector region as well as a channel region of one or more field-effect transistors.
U.S. Pat. Nos. 4,587,545, 4,587,656 and 4,608,590 teach high voltage semiconductor switches. The switches are gate-provided diodes which are formed in a dielectrically isolated region of relatively weakly doped semiconductor material. An anode and a cathode are diffused into the surface of the isolated region and the electrical connection therebetween can be broken with the aid of a gate in the surface of said region. The anode and the cathode have a type of doping which is opposite to the type of doping of the isolated region. The regions around the anode and the cathode can be depleted of charge carriers in accordance with the resurf technique, by applying appropriate voltages to the switch, which thereby becomes highly resistive in its cut-off state.